This presentation explores the critical role of comprehensive production testing at the Known Good Die (KGD) level for power semiconductor devices based on SiC technology. The manufacturing complexity and fabrication costs make die-level testing a crucial quality control step for these components. On one side, complexity brings a high potential for defects; on the other side, the need to minimize yield losses is crucial to ensure device affordability. Focusing on dynamic testing and especially on short circuit testing, we will present the specific challenges of performing these tests on KGD SiC devices, delving into the characteristics that test equipment must possess to face these challenges. The presentation will demonstrate how a comprehensive KGD test strategy enables manufacturers of SiC devices to minimize downstream production costs while achieving superior product quality and reliability.